In CMOS logic circuits, for example in inverters, use is made of both n-channel MOS transistors and p-channel MOS transistors. In this case, electrical connections between the gate electrodes of p-channel MOS transistors and n-channel MOS transistors are often made in a gate plane which is formed by structuring a layer and which, in addition to the gate electrodes, has connection elements between the gate electrodes. The gate electrodes and the connection elements between the gate electrodes are often produced as a continuous gate line. In CMOS circuits which are operated with a supply voltage of 5 volts, the gate plane is usually made of n.sup.+ -doped polysilicon or polycide.
In CMOS circuits for low-voltage/low-power applications, which are operated with a supply voltage of &lt;3 volts, the MOS transistors are optimized in such a way that they have threshold voltages .vertline.V.sub.th .vertline.&lt; 0.4 volt and at the same time low leakage currents. The gate lengths of these MOS transistors are less than 0.25 .mu.m. The concomitant high requirements on the short-channel behavior of the MOS transistors are satisfied by using a dual work-function gate technology with optimized gate work function. The term "dual work-function gate technology" means the fact that the gate electrodes for the n-channel MOS transistors and for the p-channel MOS transistors are doped differently. In the case of a gate plane with a continuous gate line which connects the various gate electrodes, this different doping in the gate electrodes leads to the danger of lateral dopant diffusion (see, for example, L. C. Parillo, IEDM 85, P 398).
The electrical properties, for example the threshold voltage V.sub.th, of the MOS transistors depends essentially on the gate doping. Lateral dopant diffusion leads to a change in the gate doping, and therefore to undesired, uncontrollable parameter shifts. In the extreme case, this can lead to reverse doping of n.sup.+ -doped or p.sup.+ -doped gate electrodes, and therefore to complete failure of the components. Furthermore, in the connection between n.sup.+ -doped gate electrodes and p.sup.+ -doped gate electrodes, with regard to a low bulk resistance, n.sup.+ -doped regions and p.sup.+ -doped regions must be directly adjacent, since a space-charge region would otherwise form.
To suppress lateral dopant diffusion in dual work-function gate technology, it has been proposed (see, for example, D. C. H. Yu et al. Int. J. High Speed Electronics and Systems, Vol. 5, p 135, 1994) not to use a continuous polysilicon connection in the gate plane between differently doped gate electrodes. Instead of this, the polysilicon gate line is divided and is electrically conductively connected via a metal bridge, for example of aluminum. Contact between the metal bridge and the gate-line segments is then made via contact holes opened in an interposed insulation layer. As an alternative, a suitable metallic conductor, for example TiN, W, Wsi.sub.2, is deposited and structured after division of the gate line. These solutions are expensive processes and to some extent require additional spatial requirements for making contact and metallization.
It has furthermore been proposed (see C. Y. Wong et al., IEDM 88, p 238) to minimize the lateral dopant diffusion in dual work-function gate technology by a reduction in the thermal loading. However, this leads to a narrow process window, for example, for the dopant activation in the gate electrode and for the planarization reflow. Furthermore, this proposed solution has not yet lead to satisfactory results.